Noel’s oxidation process has been developed over decades of experience and production expertise to configure our customized diffusion furnaces. Noel’s Founder & CTO, Leon Pearce was instrumental in developing a “Gate Oxide Process” that yielded very few gate shorts. This process has been the foundation of in the semiconductor industry for low power CMOS technology.
Utilizing low profile cantilevers, special perforated panels to facilitate cleaner operation of each run. Each lot is transferred with automated transfer equipment. These are all critical to Noel Class 100 Clean Room.
THERMAL OXIDE PROCESS (R.I. 1.46 +/-0.02)
<500A – 2KA Dry +/-10%
2KA-2.5um Wet +/-5%
WIWNU: Wafer-within-Wafer Non-Uniformity: +/-5% @ Range
One map per cassette as standard. Oxide Thickness is measured on a Noel Silicon Test Wafer with
1-50 Ohms-cm resistivity. Please note, mixed resistivity material could result in non-uniformity.
SC1/SC2/SRD is available upon request.